The present invention relates to a method of fabricating semiconductor devices, and more particularly, to a method of forming bit lines of a flash memory device.
In flash memory devices, the pattern size of lower elements is continuously being reduced. This reduction in pattern size can lead to crosstalk. To reduce the crosstalk problem, the space width of the oxide film is maximized. However, if the pitch of the metal line is reduced to obtain a higher capacity of the device, the space between the first metal lines M−1 also shrinks.
FIG. 1 is a cross-sectional view illustrating the problem with a reduction in pattern size between the bit lines of the flash memory device in the related art.
Referring to FIG. 1, metal films that generate the coupling capacitor adjacent to the bit line A include a lower word line W/L, bit lines B, C parallel to the bit line A, an upper metal line M2, and so on. The word line W/L and the bit line A are separated by a first interlayer insulating layer, but a first inter-capacitance C01 also exists therebetween.
Furthermore, the bit lines B, C adjacent to the bit line A are electrically separated by a second interlayer insulating layer, but second inter-capacitances C11 also exists therebetween. In addition, the bit line A and the upper metal line M2 are electrically separated by a third interlayer insulating layer. A third inter-capacitance C12 exists therebetween.
The coupling capacitor associated with the bit line A can be calculated as follows using the Sakurai Model. It is first assumed that the distance between the word line WL and the bit line B/L is D, the height of the bit line is T, the thickness of the bit line is W, the distance between adjacent bit lines is S, the distance between the bit line and the upper metal line is H, the first inter-capacitance is C01, the second inter-capacitance is C11, and the third inter-capacitance is C12.
                    CO        ⁢                                  ⁢        1                    ɛ        ⁢                                  ⁢        ox              =                  1.15        ⁢                  s          ⁡                      (                          W              /              D                        )                              +              2.80        ⁢                  (                      T            /            D                    )                ⁢        s        ⁢                                  ⁢        0.222            -              0.07        ⁢                  (                      T            /            D                    )                ⁢        s        ⁢                                  ⁢        0.222        ⁢                  s          ⁡                      (                          S              /              D                        )                          ⁢        s        ⁢                                  ⁢        1.34                                C        ⁢                                  ⁢        11                    ɛ        ⁢                                  ⁢        ox              =                            (                                    0.03              ⁢                              s                ⁡                                  (                                      W                    /                    D                                    )                                                      +                          0.83              ⁢                              (                                  T                  /                  D                                )                                              )                ⁢                  s          ⁡                      (                          S              /              D                        )                              -      1.34                          C        ⁢                                  ⁢        12                    ɛ        ⁢                                  ⁢        ox              =                  1.15        ⁢                  s          ⁡                      (                          W              /              H                        )                              +              2.80        ⁢                  (                      T            /            D                    )                ⁢        s        ⁢                                  ⁢        0.222            -              0.07        ⁢                  (                      T            /            D                    )                ⁢        s        ⁢                                  ⁢        0.222        ⁢                  s          ⁡                      (                          S              /              H                        )                          ⁢        s        ⁢                                  ⁢        1.34            
The total capacitance C that may be generated in the bit line by the first to third inter-capacitances according to Sakurai Model is C01+2C11+C12.
From the previous two equations, it can be seen that the thickness of the bit line and the distance between adjacent bit lines are important factors in the coupling capacitance.
That is, to reduce the bit line capacitance, the thickness (W) of the bit line can be reduced and the distance (S) between adjacent bit lines widened. However, if the thickness (W) of the bit line and the distance (S) between the bit lines are excessively reduced, the resistance of the bit line increases. It is therefore necessary to find an optimal condition considering these factors.
In recent years, the distance between the bit lines has narrowed due to higher integration of the flash memory device. Accordingly, there is a problem with increasing sensing time since the capacitance between the bit lines increases.
The term “sensing time” refers to the time it takes for the voltage of the bit line to change to the point that data in the latch circuit can be changed after performing the process of sensing variation in the voltage of the bit line when reading data and storing the read data in the page buffer in the NAND flash memory device. To improve the speed in the flash memory device, the sensing time should be reduced.